1. Field of the Invention
The present invention relates to a semiconductor circuit device, and particularly to a delay circuit device for use in generating transmitting or controlling synchronous signals (hereinafter referred to as "clock pulse").
2. Description of the Related Art
As shown in FIG. 1, a semiconductor circuit device using clock pulses according to the prior art receives an external clock pulse 401 at reception circuit 402, amplifies the clock pulse at an amplification circuit 403, and generates an internal clock pulse 405 for use in circuit 404. As a result, in the process of receiving at reception circuit 402 and amplifying at amplification circuit 403, a delay time 406 is produced between the external clock 401 and the internal clock 402, as shown in FIG. 2. This delay time 406 tends to increase with increased circuit scale of semiconductor circuit devices achieved through progress in manufacturing techniques and the growing diameter of semiconductor substrates. On the other hand, with the increase in speed of systems mounted in semiconductor circuit devices, circuit operation as well as the clock pulses employed are also increasing in speed. This increase in speed results in an increase in delay time 406 in relation to the clock cycle 407, and presents obstacles to circuit operation.
As a countermeasure, Phase-Locked Loops (hereinafter abbreviated as "PLL") have come into use. FIG. 3 shows the basic circuit structure of a PLL. At phase comparator 504, a phase error signal 506 is outputted from the phase difference of an external clock pulse 501 entering via reception circuit 502 and an internal clock pulse 505 via a delay circuit 503 having a delay equivalent to that of reception circuit 502. Phase error signal 506 becomes control signal 508 after passing through loop filter 507, and is inputted to voltage-controlled oscillator 509. At voltage-controlled oscillator 509, a clock pulse 510 is generated having a frequency corresponding to control signal 508. Clock pulse 510 is amplified at amplification circuit 511 to become internal clock pulse 505 for use in clock-controlled circuit 512. Control signal 508 controls voltage-controlled oscillator 509 such that the phase difference between external clock pulse .[.503.]. .Iadd.501 .Iaddend.and internal clock pulse 505 is eliminated, and controls voltage-controlled oscillator 509 until a phase difference is no longer detectable.
In a PLL, the delay of the internal clock pulse with respect to the external clock pulse therefore disappears, and the problem of obstacles to circuit operation due to the relative increase in delay time with respect to clock cycle can thus be avoided.
A configuration incorporating a frequency-dividing circuit in a PLL such as shown in FIG. 4 has come to be used in semiconductor circuit devices employing a clock pulse that has an integer duty ratio or a frequency that is an integer power of the frequency of an external clock.
In phase comparator 504, a phase error signal 506 is outputted from the phase difference between an external clock pulse 501 entering via reception circuit 502 and an internal clock pulse 505 entering via delay circuit 503 having a delay equal to that of reception circuit 502. Phase error signal 506 passes through loop filter 507 to become control signal 508 and is inputted to voltage-controlled oscillator 509. Voltage-controlled oscillator 509 generates a clock pulse 510 having a frequency that corresponds to control signal 508. Clock pulse 510 passes through frequency divider circuit 513 where it undergoes frequency division to become clock pulse 514. Clock pulse 514 is amplified by amplification circuit 511 to become the internal clock pulse 505 used by clock-controlled circuit 512, and clock pulse 510 is amplified by amplification circuit 515 to become the internal clock pulse 516 used by clock-controlled circuit 512. Control signal 508 controls voltage-controlled oscillator 509 so as to eliminate the phase difference between external clock pulse .[.503.]. .Iadd.501 .Iaddend.and internal clock pulse 505. Internal clock pulse 505 becomes a clock pulse having the same phase and cycle as external clock pulse 503, and moreover, having an integer duty ratio. Clock 516 has the same frequency as internal clock pulse 505 before frequency division, and therefore, becomes a clock pulse having a frequency-divided inverse frequency with respect to external clock pulse .[.503.]. .Iadd.501.Iaddend..